PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 420

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Time Slot Bit Select 1 (Read/Write)
Value after reset: FF
TSBS1
TSB1(7:0) =
Time Slot Bit Select 2 (Read/Write)
Value after reset: FF
TSBS2
TSB2(7:0)
User’s Manual
Hardware Description
TSB17
TSB27
7
7
TSB16
TSB26
Time Slot Bit Selection - HDLC Channel 1
Only bits selected by this register are used for HDLC channel 1 in
selected time slots. Time slot selection is done by setting the
appropriate bits in registers TTR(4:1) and RTR(4:1) independently
for receive and transmit direction. Bit selection is common to receive
and transmit direction. By default all bit positions within the selected
time slot(s) are enabled.
TSB1x = 0 to bit position x in selected time slot(s) is not used for
HDLC channel 1 reception and transmission.
TSB1x = 1 to bit position x in selected time slot(s) is used for HDLC
channel 1 reception and transmission.
Time Slot Bit Selection - HDLC Channel 2
Only bits selected by this register are used for HDLC channel 2 in
selected time slots. Time slot selection is done by setting the
appropriate bits in register TSS2. Bit selection is common to receive
and transmit direction. By default all bit positions within the selected
time slot are enabled.
TSB2x=0 to bit position x in selected time slot(s) is not used for
HDLC channel 2 reception and transmission.
TSB2x=1 to bit position x in selected time slot(s) is used for HDLC
channel 2 reception and transmission.
H
H
TSB15
TSB25
TSB14
TSB24
420
TSB13
TSB23
TSB12
TSB22
TSB11
TSB21
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
TSB10
TSB20
0
0
FALC
(A1)
(A2)
®
56