PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 45

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 4
Pin or
Ball No.
60 (B8)
61 (A9)
62 (A8)
63 (B7)
User’s Manual
Hardware Description
Name
XPA
XPB
XBC
XPD
Pin Definitions - System Interface (cont’d)
Pin
Type
O
O
I
I
O
O
Buffer
Type
PU
PU
Function
Data Link Bit Transmit (DLX)
PC(1:4).XPC(3:0) = 0110
E1: Marks the S
T1/J1: This output provides a 4-kHz signal
Transmit Clock (XCLK)
PC(1:4).XPC(3:0) = 0111
Transmit line clock of 2.048 MHz (E1) or
1.544 MHz (T1/J1) derived from SCLKX/R,
RCLK or generated internally by DCO
circuitries.
Transmit Line Tristate (XLT)
PC(1:4).XPC(3:0) = 1000
A high level on this port sets the transmit lines
XL1/2 or XDOP/N into tristate mode. This pin
function is logically ored with register bit
XPM2.XLT.
General Purpose Input (GPI)
PC(1:4).XPC(3:0) = 1001
The digital signal level applied externally can
be read through a status register.
For unused XPAx pins this configuration is
recommended.
General Purpose Output High (GPOH)
PC(1:4).XPC(3:0) = 1010
A fixed high output level is driven.
General Purpose Output Low (GPOL)
PC(1:4).XPC(3:0) = 1011
A fixed low output level is driven.
45
stream on XDI. The S
positions in time slot 0 of every frame
not containing the frame alignment
signal are selected by register
XC0.SA8E to XC0.SA4E.
which marks the DL-bit position within
the data stream on XDI (in ESF mode
only).
a
(8:4)-bits within the data
B
B
B
B
B
B
a
External Signals
(8:4)-bit
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56