HD6432646 Hitachi, HD6432646 Datasheet - Page 1000

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

BCRA—Break Control Register A
BCRB—Break Control Register B
966
Notes:
Condition Match Flag A
Bit
Initial value
Read/Write
0 [Clearing condition]
1
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied
CPU Cycle/DTC Cycle Select A
0 PC break is performed when CPU is bus master
1
BCRB is the channel B break control register.
The bit configuration is the same as for BCRA.
* Only a 0 may be written to this bit to clear the flag.
PC break is performed when CPU or DTC is bus master
Break Address Mask Register
0
1
R/(W)*
CMFA
0
1
0
1
7
0
0
1
0
1
0
1
0
1
Break Condition Select
All BARA bits are unmasked and included in break conditions
BAA0 (lowest bit) is masked, and not included in break conditions
BAA1–0 (lower 2 bits) are masked, and not included in break conditions
BAA2–0 (lower 3 bits) are masked, and not included in break conditions
BAA3–0 (lower 4 bits) are masked, and not included in break conditions
BAA7–0 (lower 8 bits) are masked, and not included in break conditions
BAA11–0 (lower 12 bits) are masked, and not included in break conditions
BAA15–0 (lower 16 bits) are masked, and not included in break conditions
0
1
CDA
R/W
0
1
0
1
6
0
Instruction fetch is used as break condition
Data read cycle is used as break condition
Data write cycle is used as break condition
Data read/write cycle is used as break condition
BAMRA2
R/W
5
0
BAMRA1
R/W
4
0
BAMRA0
H'FE08
H'FE09
R/W
3
0
Break Interrupt Enable
0 PC break interrupts are disabled
1
PC break interrupts are enabled
CSELA1
R/W
2
0
CSELA0
R/W
1
0
BIEA
R/W
0
0
PBC
PBC