HD6432646 Hitachi, HD6432646 Datasheet - Page 720

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

686
Note: Use a 10 s write pulse for additional programming.
Note *6: Write Pulse Width
Figure 20-11 Program/Program-Verify Flowchart (128-Byte Programming)
Number of Writes n
Write pulse application subroutine
1000
998
999
Notes: *1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
10
11
12
13
Clear PSU bit in FLMCR1
Reprogram data storage
Additional-programming
1
2
3
4
5
6
7
8
9
Sub-Routine Write Pulse
Reprogram Data Computation Table
Set PSU bit in FLMCR1
Program data storage
Clear P bit in FLMCR1
Set P bit in FLMCR1
data storage area
Original Data
area (128 bytes)
area (128 bytes)
Wait (t
Wait (t
(128 bytes)
*2 Verify data is read in 16-bit (word) units.
*3 Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
*4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
*5 A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note *6 for details of the pulse widths. When writing of
*7 The wait times and value of N are shown in section 23.7, Flash Memory characteristics.
WDT enable
Wait (t
Wait (t
Disable WDT
(D)
RAM
End Sub
0
0
1
1
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
spsu
cpsu
Write Time (tsp) sec
sp
cp
) s
) s
) s
) s
Verify Data
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
(V)
0
1
0
1
Reprogram Data
*
*
*
*
Start of programming
End of programming
7
5
7
7
*
7
(X)
Increment address
1
0
1
1
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
No
Comments
Transfer reprogram data to reprogram data area
Additional-programming data computation
Write Pulse (Additional programming)
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Wait (t
Wait (t
Read verify data
Wait (t
Wait (t
Wait (t
Yes
Yes
Write data =
verify data?
Write pulse
Yes
128-byte
START
6 n ?
m= 0 ?
m= 0
6 n?
n= 1
sswe
cswe
spvr
Additional-Programming Data Computation Table
spv
cpv
Reprogram Data
Yes
Yes
Sub-Routine-Call
Sub-Routine-Call
) s
) s
) s
) s
) s
(X')
0
0
1
1
No
No
No
Verify Data
*
*
*
*
No
7
*
*
(V)
See Note *6 for pulse width
7
7
2
0
1
0
1
3
7
*
*
*
4
1
4
*
*
m = 1
1
4
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Programming Data (Y)
Clear SWE bit in FLMCR1
Programming failure
Wait (t
Additional-
0
1
1
1
n
cswe
(N)?
Yes
) s
*
7
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
No
n
Comments
n + 1
*
Reprogram
7