HD6432646 Hitachi, HD6432646 Datasheet - Page 431

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

11.2.6
PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping
operation for each group.
The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB
and the non-overlap margin is set in TGRA. The output values change at compare match A and B.
For details, see section 11.3.4, Non-Overlapping Pulse Output.
PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output
group 3 (pins PO15 to PO12).
Bit 7
G3INV
0
1
Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output
group 2 (pins PO11 to PO8).
Bit 6
G2INV
0
1
Bit
Initial value :
R/W
PPG Output Mode Register (PMR)
Description
Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
Description
Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
:
:
G3INV
R/W
7
1
G2INV
R/W
6
1
G1INV
R/W
5
1
G0INV
R/W
4
1
G3NOV
R/W
3
0
G2NOV
R/W
2
0
G1NOV
R/W
1
0
(Initial value)
(Initial value)
G0NOV
R/W
0
0
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