HD6432646 Hitachi, HD6432646 Datasheet - Page 210

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

(3) Relationship between Chip Select (CS*) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal*. An
example is shown in figure 7-17.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Note: * The CS signal is generated externally rather than inside the LSI device.
176
CS* (area A)
CS* (area B)
Note: * The CS signal is generated externally rather than inside the LSI device.
Address bus
Data bus
HWR
RD
ø
Figure 7-17 Relationship between Chip Select (CS) * and Read (RD)
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS0 = 0)
T
2
T
floating time
Long output
3
Bus cycle B
T
1
T
2
Data
collision
CS* (area A)
CS* (area B)
Address bus
Data bus
HWR
RD
ø
T
(b) Idle cycle inserted
1
Bus cycle A
(Initial value ICIS0 = 1)
T
2
T
3
T
I
Bus cycle B
T
1
T
2