HD6432646 Hitachi, HD6432646 Datasheet - Page 159

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

5.5.4
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
5.5.5
When operating by clock input, acceptance of input to an IRQ pin is synchronized with the clock.
In software standby mode, the input is accepted asynchronously. For details on the input
conditions, see section 23.4.2, Control Signal Timing.
5.6
5.6.1
The DTC can be activated by an interrupt. In this case, the following options are available:
For details of interrupt requests that can be used with to activate the DTC, see section 8, Data
Transfer Controller (DTC).
5.6.2
Figure 5-9 shows a block diagram of the DTC interrupt controller.
Interrupt request to CPU
Activation request to DTC
Selection of a number of the above
L1:
Interrupts during Execution of EEPMOV Instruction
IRQ Interrupts
DTC Activation by Interrupt
Overview
Block Diagram
EEPMOV.W
BNE
MOV.W
L1
R4,R4
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