HD6432646 Hitachi, HD6432646 Datasheet - Page 23

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

7.7
7.8
7.9
Section 8
8.1
8.2
8.3
8.4
8.5
Section 9
9.1
9.2
Write Data Buffer Function ............................................................................................... 178
Bus Arbitration .................................................................................................................. 179
7.8.1
7.8.2
7.8.3
Resets and the Bus Controller............................................................................................ 180
Overview............................................................................................................................ 181
8.1.1
8.1.2
8.1.3
Register Descriptions......................................................................................................... 184
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation ........................................................................................................................... 192
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10 Number of DTC Execution States........................................................................ 206
8.3.11 Procedures for Using DTC ................................................................................... 208
8.3.12 Examples of Use of the DTC................................................................................ 209
Interrupts............................................................................................................................ 212
Usage Notes ....................................................................................................................... 212
Overview............................................................................................................................ 213
Port 1.................................................................................................................................. 221
9.2.1
9.2.2
Overview .............................................................................................................. 179
Operation .............................................................................................................. 179
Bus Transfer Timing ............................................................................................ 179
Data Transfer Controller (DTC) ......................................................181
Features ................................................................................................................ 181
Block Diagram...................................................................................................... 182
Register Configuration ......................................................................................... 183
DTC Mode Register A (MRA)............................................................................. 184
DTC Mode Register B (MRB) ............................................................................. 186
DTC Source Address Register (SAR) .................................................................. 187
DTC Destination Address Register (DAR) .......................................................... 187
DTC Transfer Count Register A (CRA) .............................................................. 187
DTC Transfer Count Register B (CRB) ............................................................... 188
DTC Enable Registers (DTCER) ......................................................................... 188
DTC Vector Register (DTVECR) ........................................................................ 189
Module Stop Control Register A (MSTPCRA).................................................... 190
Overview .............................................................................................................. 192
Activation Sources................................................................................................ 194
DTC Vector Table ................................................................................................ 195
Location of Register Information in Address Space ............................................ 199
Normal Mode........................................................................................................ 200
Repeat Mode ........................................................................................................ 201
Block Transfer Mode............................................................................................ 202
Chain Transfer...................................................................................................... 204
Operation Timing ................................................................................................. 205
I/O Ports ...........................................................................................213
Overview .............................................................................................................. 221
Register Configuration ......................................................................................... 222
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