HD6432646 Hitachi, HD6432646 Datasheet - Page 710

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be
a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 19,200,
9,600 or 4,800 bps to operate the SCI properly.
Table 20-6 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI bit rate is possible. The boot program should be executed within this system
clock range.
Table 20-6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Host Bit Rate
19,200 bps
9,600 bps
4,800 bps
Note: The system clock frequency used in boot mode is generated by an external crystal oscillator
676
element. PLL frequency multiplication is not used.
Possible
Start
bit
D0
System Clock Frequency for Which Automatic Adjustment
of LSI Bit Rate is Possible
16–20 MHz
8–20 MHz
4–20 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit