HD6432646 Hitachi, HD6432646 Datasheet - Page 101

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

2.8.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2-7
Priority
High
Low
Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception-handling is not
*2 Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
*3 Trap instruction exception handling is always accepted, in the program execution state.
Exception-Handling State
executed at the end of the RTE instruction.
or immediately after reset exception handling.
Type of Exception
Reset
Trace
Interrupt
Trap instruction
Exception Handling Types and Priority
Detection Timing
Synchronized with clock
End of instruction
execution or end of
exception-handling
sequence
End of instruction
execution or end of
exception-handling
sequence
When TRAPA instruction
is executed
*1
*2
Start of Exception Handling
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Exception handling starts when
a trap (TRAPA) instruction is
executed
* 3
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