HD6432646 Hitachi, HD6432646 Datasheet - Page 612

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt
source settings and receive message specifications must be made. Interrupt source settings are
made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a
message, the identifier must be set in advance in the message control (MCx[1]–MCx[8]) for the
receiving mailbox. When a message is received, all the bits in the receive message identifier are
compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox
0 (MB0) has a local acceptance filter mask (LAFM) that allows Don’t Care settings to be made.
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CPU interrupt source settings
When transmitting, transmission acknowledge and transmission abort acknowledge interrupts
can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR).
When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt
register (IRR) interrupts can be masked in the interrupt mask register (IMR).
Arbitration field setting
In the arbitration field, the identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) of the
message to be received is set. If all the bits in the set identifier do not match, the message is not
stored in a mailbox.
Example: Mailbox 1
Local acceptance filter mask (LAFM) setting
The local acceptance filter mask is provided for mailbox 0 (MB0) only, enabling a Don’t Care
specification to be made for all bits in the received identifier. This allows various kinds of
messages to be received.
Example: Mailbox 0
Only one kind of message identifier can be received by MB1
Identifier 1:
LAFM
A total of four kinds of message identifiers can be received by MB0
Identifier 1:
Identifier 2:
Identifier 3:
Identifier 4:
010_1010_1010 (standard identifier)
010_1010_1010
010_1010_1010 (standard identifier)
000_0000_0011 (0: Care, 1: Don’t Care)
010_1010_1000
010_1010_1001
010_1010_1010
010_1010_1011