HD6432646 Hitachi, HD6432646 Datasheet - Page 456

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

12.2.3
Note: * Can only be written with 0 for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2646 Series if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
0
1
Note: * The modules within the H8S/2646 Series are not reset, but TCNT and TCSR within the
Bit 5—Reserved: Always read as 0. Can only be written with 0.
Bits 4 to 0—Reserved: Always read as 1. Not writable.
422
Bit
Initial value :
R/W
WDT are reset.
see section 12.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Description
[Clearing condition]
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Description
Reset signal is not generated if TCNT overflows*
Reset signal is generated if TCNT overflows
:
:
WOVF
R/(W)*
7
0
RSTE
R/W
6
0
R/W
—
5
0
—
—
4
1
—
—
3
1
—
—
2
1
—
—
1
1
(Initial value)
(Initial value)
—
—
0
1