HD6432646 Hitachi, HD6432646 Datasheet - Page 185

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
0
1
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
7.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function.
BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bit 5—Reserved: It is always read as 0. Cannot be written to.
Bit 4—Reserved: Only 0 should be written to this bit.
Bit 3—Reserved: Only 1 should be written to this bit.
Bit 2—Reserved: Only 0 should be written to this bit.
Bit
Initial value
R/W
Bus Control Register L (BCRL)
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
Description
Max. 4 words in burst access
Max. 8 words in burst access
:
:
:
R/W
—
7
0
R/W
—
6
0
—
—
5
0
R/W
—
4
0
R/W
—
3
1
R/W
—
2
0
WDBE
R/W
1
0
(Initial value)
(Initial value)
WAITE
R/W
0
0
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