HD6432646 Hitachi, HD6432646 Datasheet - Page 596

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

15.3
This LSI device is equipped with 2-channel HCAN modules, which are controlled independently.
Both modules have identical specifications, and they are controlled in the same manner.
15.3.1
The HCAN can be reset by a hardware reset or software reset.
Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization
is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state
bit (GSR3) in GSR within the HCAN (hardware reset). At the same time, all internal registers are
initialized. However mailbox contents are retained. A flowchart of this reset is shown in figure
15-4.
Note: * In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the
Software Reset (Write to MCR0): In normal operation initialization is performed by setting the
MCR reset request bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN
controller is performing a communication operation (transmission or reception), the initialization
state is not entered until the message has been completed. During initialization, the reset state bit
(GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are
initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in
figure 15-5.
15.3.2
After a hardware reset, the following initialization processing should be carried out:
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and
the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is
exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN
automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up
sequence then begins, and communication with the CAN bus is possible as soon as the sequence
ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.
562
IRR0 bit in the interrupt register (IRR) clearing
Bit rate setting
Mailbox transmit/receive settings
Mailbox (RAM) initialization
Message transmission method setting
HCAN enters the module stop state.
Operation
Hardware and Software Resets
Initialization after Hardware Reset