HD6432646 Hitachi, HD6432646 Datasheet - Page 1047

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TIOR0L—Timer I/O Control Register 0L
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
Bit
Initial value
Read/Write
Notes: *1
TGR0D I/O Control
register operates as a buffer register.
0
1
0
1
0
1
*2
0
1
0
1
0
1
*
When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
0
1
0
1
*
*
IOD3
R/W
TGR0D is
output
compare
register
TGR0D is
input
capture
register
7
0
*2
*2
Note: *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
TGR0C I/O Control
0
1
IOD2
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
0
1
0
1
*
*
IOD1
R/W
TGR0C is
output
compare
register
TGR0C is
input
capture
register
5
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*1
*1
IOD0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
R/W
4
0
*1
H'FF13
IOC3
R/W
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*: Don't care
IOC2
R/W
2
0
IOC1
R/W
1
0
*: Don't care
IOC0
R/W
0
0
TPU0
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