HD6432646 Hitachi, HD6432646 Datasheet - Page 603
HD6432646
Manufacturer Part Number
HD6432646
Description
(HD64F264x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432646.pdf
(1155 pages)
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Mailbox (Message Control/Data (MCx[x], MDx[x])) Initial Settings: After power is supplied,
all registers and RAM (message control/data, control registers, status registers, etc.) are initialized.
Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined.
Initial values must therefore be set in all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: Either of the following message transmission
methods can be selected with the message transmission method bit (MCR2) in the master control
register (MCR):
a. Transmission order determined by message identifier priority
b. Transmission order determined by mailbox number priority
When a is selected, if a number of messages are designated as waiting for transmission (TXPR =
1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored
in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit
buffer, and message transmission is performed when the transmission right is acquired. When the
TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found
and stored in the transmit buffer.
When b is selected, if a number of messages are designated as waiting for transmission (TXPR =
1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:
mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit
buffer, and message transmission is performed when the bus is acquired.
15.3.3
Message transmission is performed using mailboxes 1 to 15. The transmission procedure is
described below, and a transmission flowchart is shown in figure 15-7.
Initialization (after hardware reset only)
Interrupt and transmit data settings
a. IRR0 bit in the intereupt register (IRR0) clearing
b. Bit rate settings
c. Mailbox transmit/receive settings
d. Mailbox initialization
e. Message transmission method setting
a. CPU interrupt source setting
b. Arbitration field setting
c. Control field setting
d. Data field setting
Transmit Mode
569
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