HD6432646 Hitachi, HD6432646 Datasheet - Page 526

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Restrictions on Use of DTC
Operation in Case of Mode Transition
492
When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 13-22)
When RDR is read by the DTC, be sure to set the activation source to the relevant SCI
reception end interrupt (RXI).
Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.
TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby
mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and
becomes high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started by
setting TE to 1 again, and performing the following sequence: SSR read
TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode,
the procedure must be started again from initialization. Figure 13-23 shows a sample flowchart
for mode transition during transmission. Port pin states are shown in figures 13-24 and 13-25.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop mode, software standby mode,
watch mode, subactive mode, or subsleep mode transition. To perform transmission with the
DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start
DTC transmission.
SCK
TDRE
Serial data
Note: When operating on an external clock, set t >4 clocks.
Figure 13-22 Example of Clocked Synchronous Transmission by DTC
t
LSB
D0
D1
D2
D3
D4
D5
D6
TDR write
D7