HD6432646 Hitachi, HD6432646 Datasheet - Page 782

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

22.9
22.9.1
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode.
In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are
also stopped. The contents of the CPU’s internal registers, the data in internal RAM, and the
statuses of the internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control
PWM) and I/O ports are retained.
22.9.2
Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or
IRQ0 to IRQ5), or signals at the RES or STBY pins.
Exiting Sub-Sleep Mode by Interrupts: When an interrupt occurs, sub-sleep mode is exited and
interrupt exception processing starts.
enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting
modules, the interrupt enable register has been set to disable the reception of that interrupt, or is
masked by the CPU.
Exiting Sub-Sleep Mode by RES: For exiting sub-sleep mode by the RES pins, see, Clearing
with the RES pins in section 22.6.2, Clearing Software Standby Mode.
Exiting Sub-Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is
made to hardware standby mode.
748
In the case of IRQ0 to IRQ5 interrupts, sub-sleep mode is not cancelled if the corresponding
Sub-Sleep Mode
Sub-Sleep Mode
Exiting Sub-Sleep Mode