HD6432646 Hitachi, HD6432646 Datasheet - Page 700

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

20.4
The registers used to control the on-chip flash memory when enabled are shown in table 20-2.
Table 20-2 Register Configuration
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register FLPWCR
Notes: *1 Lower 16 bits of the address.
20.5
20.5.1
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE bit to 1 when
FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000 to H'1FFFF is
entered by setting SWE bit to 1 when FWE = 1, then setting the PSU bit, and finally setting the P
bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting SWE bit to 1 when FWE
= 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in
hardware standby mode and software standby mode. Its initial value is H'80 when a high level is
input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled,
a read will return H'00, and writes are invalid.
Writes are enabled only in the following cases: Writes to bit SWE of FLMCR1 enabled when
FWE = 1, to bits ESU, PSU, EV, and PV when FWE = 1 and SWE = 1, to bit E when FWE = 1,
SWE = 1 and ESU = 1, and to bit P when FWE = 1, SWE = 1, and PSU = 1.
666
*2 When a high level is input to the FWE pin, the initial value is H'80.
*3 When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
*4 FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.
Register Configuration
Register Descriptions
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is not set, these registers are initialized to H'00.
Use byte access on these registers.
Abbreviation
FLMCR1
FLMCR2
EBR1
EBR2
RAMER
* 4
* 4
*4
* 4
* 4
* 4
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
H'00
H'00
H'00
H'00
H'00
H'00
*2
*3
*3
*3
Address
H'FFA8
H'FFA9
H'FFAA
H'FFAB
H'FEDB
H'FFAC
*1