HD6432646 Hitachi, HD6432646 Datasheet - Page 452

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
Bit 7
OVF
0
1
In interval timer mode, the OVF flag can be cleared in the interval timer interrupt service routine
by reading TCSR while OVF = 1, then writing 0 to OVF, in accordance with the OVF flag
clearing conditions.
However, if conflict occurs between the OVF flag setting timing and OVF flag read timing when
interval timer interrupts are disabled and the OVF flag is polled, it has been found that in some
cases the read of OVF = 1 is not recognized.
In this case, the OVF flag clearing conditions can be reliably met by reading the OVF = 1 state
two or more times. In the above example, therefore, the OVF = 1 state should be read at least
twice before clearing the OVF flag.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. When TCNT overflows, WDT0 issues an internal reset if bit RSTE of the reset
control/status register (RSTCSR) is set to 1. In the interval timer mode, WDT0 sends a WOVI
interrupt request to the CPU. WDT1, on the other hand, requests a reset or an NMI interrupt from
the CPU if the watchdog timer mode is chosen, whereas it requests a WOVI interrupt from the
CPU if the interval timer mode is chosen.
418
section 12.2.4, Notes on Register Access.
Description
[Clearing conditions]
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Cleared when 0 is written to the TME bit (Only applies to WDT1)
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
(Initial value)