HD6432646 Hitachi, HD6432646 Datasheet - Page 1100

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCSR1—Timer Control/Status Register 1
1066
Note: * Only a 0 may be written to this bit to clear the flag.
Overflow Flag
0
1
Bit
Initial value
Read/Write
Timer Mode Select
[Clearing conditions]
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
0
1
TCSR1 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
Cleared when 0 is written to the TME bit (Only applies to WDT1)
Cleared by reading TCSR when OVF = 1, then write 0 in OVF
Timer Enable
Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows
Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows
0
1
Prescaler Select
TCNT is initialized to H'00 and halted
TCNT counts
0
1
Reset or NMI
The TCNT counts frequency-
division clock pulses of the
ø based prescaler (PSM)
The TCNT counts frequency-
division clock pulses of the
ø SUB-based prescaler (PSS)
0
1
R/(W)*
NMI request
Internal reset request
OVF
7
0
WT/IT
R/W
6
0
TME
R/W
5
0
Clock Select 2 to 0
Note: * An overflow period is the time interval between the start of
PSS
0
1
CKS2
counting up from H'00 on the TCNT and the occurrence of a
TCNT overflow.
PSS
R/W
0
1
0
1
4
0
CKS1 CKS0
H'FFA2(W), H'FFA2(R)
0
0
1
0
1
1
0
1
RST/NMI
R/W
3
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
øSUB/2
øSUB/4
øSUB/8
øSUB/16
øSUB/32
øSUB/64
øSUB/128
øSUB/256
Clock
CKS2
R/W
2
0
(where ø SUB = 32.768 kHz)
CKS1
(where ø = 20 MHz)
R/W
Overflow Period*
1
0
25.6 s
819.2 s
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
CKS0
R/W
0
0
WDT1