HD6432646 Hitachi, HD6432646 Datasheet - Page 631

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

16.3
ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte
value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADDR. always read the upper byte before the lower byte. It is possible to read only
the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 16-2 shows the data flow for ADDR access.
Bus master
(H'AA)
Bus master
(H'40)
Interface to Bus Master
Lower byte read
Upper byte read
Figure 16-2 ADDR Access Operation (Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
ADDRnL
ADDRnL
(H'40)
(H'40)
TEMP
(H'40)
TEMP
(H'40)
Module data bus
Module data bus
(n = A to D)
(n = A to D)
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