HD6432646 Hitachi, HD6432646 Datasheet - Page 620

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

4. Error counters
5. Register access
6. HCAN medium-speed mode
7. Register hold during standby
8. Usage of bit manipulation instructions
9. HTxD pin output in error passive state
10. Transition to HCAN sleep mode
11. Message transmission cancellation (TxCR)
12. TxCR in the bus off state
586
not set by reception completion, transmission completion, or transmission cancellation for the
set mailboxes.
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set.
Byte or word access can be used on all HCAN registers. Longword access cannot be used.
In medium-speed mode, the HCAN register cannot be read from or written to.
All registers in the HCAN are initialized on entering hardware standby or software modes.
The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to
clear a flag.
When clearing a flag, use the MOV instruction to write 1 to only the bit that is to be cleared.
If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN
is in the error active state, the HTxD pin will output 0 continuously while in the error passive
state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error
warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1
state by the HxRD pin monitor.
The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after
an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting
MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps,
a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode
transition, release the HCAN sleep mode by clearing MCR5 to 0.
If all the following conditions are met when cancellation of a transmission message is
performed by means of TxCR of the HCAN, the TxCR or TxPR bit indicating cancellation is
not cleared even though internal transmission is canceled.
When canceling a message using TxCR, 1 should be written continuously until TxCR or TxPR
becomes 0.
If TxPR is set before the HCAN goes to the bus off state, and a transition is made to the bus off
state with transmission incomplete, cancellation will be performed even if TxCR is set during
the bus off period, and the message will be transmitted after a transition to the error active
state.