HD6432646 Hitachi, HD6432646 Datasheet - Page 563

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

[6] If an error signal is sent back from the receiving end after transmission of one frame is
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
Retransfer operation when SCI is in transmit mode
Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode.
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
is received.
a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI interrupt request is generated.
If data transfer by the DTC by means of the TXI source is enabled, the next data can be written
to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is
automatically cleared to 0.
Ds
TDRE
TEND
FER/ERS
RDRF
PER
Ds
Transfer to TSR from TDR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
nth transfer frame
Figure 14-12 Retransfer Operation in SCI Transmit Mode
Figure 14-11 Retransfer Operation in SCI Receive Mode
nth transfer frame
[6]
[2]
[1]
[7]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
Retransferred frame
Retransferred frame
(DE)
[8]
(DE)
[9]
[4]
[3]
Ds D0 D1 D2 D3 D4
Ds D0 D1 D2 D3 D4
Transfer
frame n+1
Transfer to TSR
from TDR
Transfer
frame n+1
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