HD6432646 Hitachi, HD6432646 Datasheet - Page 209

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
CS* (area A)
CS* (area B)
Address bus
Note: * The CS signal is generated externally rather than inside the LSI device.
RD
Possibility of overlap between
CS (area B) and RD
ø
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
Figure 7-16 Example of Idle Cycle Operation (2)
2
T
3
Bus cycle B
T
1
T
2
CS* (area A)
CS* (area B)
Address bus
RD
ø
T
1
Bus cycle A
(b) Idle cycle inserted
T
(Initial value ICIS1 = 1)
2
T
3
T
I
Bus cycle B
T
1
T
2
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