AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 100

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

18.3.5
18.3.6
18.4
Base Address: 0xFFFFFF00
Table 18-1.
Offset
0x00
0x04
0x08
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status
register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and
include:
In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as search-
ing for which address generated the abort would require disassembling the instructions and full knowledge of the
processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM pro-
cessor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is
probable that several aborts have occurred during this time. Thus, in this case, it is preferable to use the content of
the Abort Link register of the ARM processor.
The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the Flash block
with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buf-
fers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of
commands.
The Memory Controller features a Misalignment Detector that checks the consistency of the accesses.
For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are
checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-
word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the
accesses of the ARM processor when it is fetching instructions are not checked.
The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particu-
larly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status Register and the address of the instruction generating the
misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bug is
simplified.
Memory Controller (MC) User Interface
• the size of the request (field ABTSZ)
• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
• whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit
• the source of the access leading to the last abort (bits MST0 and MST1)
• whether or not an abort occurred for each master since the last read of the register (bit SVMST0 and SVMST1)
Embedded Flash Controller
Misalignment Detector
MISADD)
unless this information is loaded in MST bits
Register Mapping
Register
MC Remap Control Register
MC Abort Status Register
MC Abort Address Status Register
MC_AASR
MC_RCR
MC_ASR
Name
SAM7S Series [DATASHEET]
Read-only
Read-only
Write-only
Access
6175M–ATARM–26-Oct-12
Reset
0x0
0x0
100