AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 645
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AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Price
Company:
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
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40.10.3.2
40.10.3.3
40.10.4
40.10.4.1
40.10.5
40.10.5.1
When Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the period register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the cor-
responding bit might be cleared. This can lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
Real Time Timer (RTT)
USART: Universal Synchronous Asynchronous Receiver Transmitter
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
PWM: Update when PWM_CPRDx = 0
PWM: Counter Start Value
RTT: Possible Event Loss when Reading RTT_SR
USART: DCD is active High instead of Low
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
645
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