AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 375

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

31.6.3.8
Table 31-7
function of the Baud Rate.
Table 31-7.
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition
on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises
and can generate an interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of
the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled
and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit
counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time
a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user
can either:
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before
the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a
wait of the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation
of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 31-16
• Stop the counter clock until a new character is received. This is performed by writing the Control Register
• Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload
(US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is
received will not provide a time-out. This prevents having to handle an interrupt before a character is received
and allows waiting for the next idle state on RXD after a frame is received.
and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the
value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example
when no key is pressed on a keyboard.
Receiver Time-out
Baud Rate
indicates the maximum length of a timeguard period that the transmitter can handle in relation to the
115200
Bit/sec
14400
19200
28800
33400
56000
57600
1 200
9 600
shows the block diagram of the Receiver Time-out feature.
Maximum Timeguard Length Depending on Baud Rate
Bit time
69.4
52.1
34.7
29.9
17.9
17.4
833
104
8.7
µs
Timeguard
SAM7S Series [DATASHEET]
212.50
26.56
17.71
13.28
8.85
7.63
4.55
4.43
2.21
ms
6175M–ATARM–26-Oct-12
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