AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 217

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

26.3
26.3.1
26.3.2
26.3.3
26.4
26.4.1
Product Dependencies
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the pro-
grammer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
Depending on product integration, the Debug Unit clock may be controllable through the Power Management Con-
troller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the
peripheral identifier used for this purpose is 1.
Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug
Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with
the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in
1. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.
UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with
parity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common
baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the imple-
mented features are compatible with those of a standard USART.
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate
Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART
remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud
rate is Master Clock divided by (16 x 65536).
Figure 26-2. Baud Rate Generator
I/O Lines
Power Management
Interrupt Source
Baud Rate Generator
MCK
16-bit Counter
CD
Baud Rate
OUT
0
=
--------------------- -
16
CD
>1
1
0
MCK
×
CD
Divide
by 16
SAM7S Series [DATASHEET]
Baud Rate
Receiver
Sampling Clock
Clock
6175M–ATARM–26-Oct-12
Figure 26-
217