AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 338

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

30.9.4.2
30.9.4.3
30.9.4.4
30.9.5
30.9.5.1
Figure 30-24. Read Access Ordered by a MASTER
EOSVACC
SVREAD
TXRDY
SVACC
NACK
See
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as
soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when
reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR
is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the
new address programming sequence.
See
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave
address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR
register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 30-24 on page 338
TWD
Data Transfer
Figure 30-24 on page
Figure 30-25 on page
Figure 30-27 on page 341
Figure 30-26 on page
Write Sequence
Clock Synchronization Sequence
General Call
Read Operation
S
ADR
TWI answers with a NACK
SADR does not match,
R
NA
describes the write operation.
338.
339.
339.
DATA
and
NA
Figure 30-28 on page
P/S/Sr
Write THR
SADR
TWI answers with an ACK
SADR matches,
R
SVREAD has to be taken into account only while SVACC is active
342.
A
DATA
A
SAM7S Series [DATASHEET]
ACK/NACK from the Master
A
DATA
6175M–ATARM–26-Oct-12
NA
S/Sr
Read RHR
338