AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 414

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

32.6.1.4
32.6.2
Figure 32-8. Transmitter Block Diagram
32.6.3
Transmitter Clock
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK
or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock
speed allowed on the RK pin is:
In addition, the maximum clock speed allowed on the TK pin is:
A transmitted frame is triggered by a start event and can be followed by synchronization data before data
transmission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR).
The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR).
Sync” on page 417.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode
selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift
register according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR.
When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in
SSC_SR and additional data can be loaded in the holding register.
A received frame is triggered by a start event and can be followed by synchronization data before data
transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR).
Transmitter Operations
Receiver Operations
SSC_TFMR.DATLEN
Serial Clock Ratio Considerations
– Master Clock divided by 2 if Receiver Frame Synchro is input
– Master Clock divided by 3 if Receiver Frame Synchro is output
– Master Clock divided by 6 if Transmit Frame Synchro is input
– Master Clock divided by 2 if Transmit Frame Synchro is output
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
RF
Selector
Start
TF
SSC_TFMR.MSBF
SSC_THR
SSC_TFMR.DATDEF
Transmit Shift Register
0
1
SSC_TSHR
1
0
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.FSLEN
SSC_CR.TXEN
SSC_CR.TXDIS
SSC_SR.TXEN
SAM7S Series [DATASHEET]
See “Start” on page 415.
See “Start” on page 415.
6175M–ATARM–26-Oct-12
See “Frame
TD
414