AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 616

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.6.2.10
40.6.2.11
40.6.3
40.6.3.1
40.6.4
40.6.4.1
If “x” and “y” are two successively converted channels and “z” is yet another enabled channel (“z” being neither “x”
nor “y”), reading CDR on channel “z” at the same instant as an end of conversion on channel “y” automatically
clears EOC[x] instead of EOC[z].
None.
If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after
a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register
(SLEEP) then ADC Control Register (START bit field); to start an analog-to-digital conversion, in order put ADC
into sleep mode at the end of this conversion.
If the Flash is operating without wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 19 MHz.
If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 19 MHz.
If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 25 MHz.
If the Flash is operating with three wait states, the frequency of the Master Clock MCK must be lower than 3 MHz
or higher than 38 MHz.
If these constraints are not respected, the correct operation of the system cannot be guaranteed and either data or
prefetch abort might occur.
The maximum operating frequencies (at 30 MHz @ 0 Wait States and 55 MHz @ 1 Wait State) as stated in
Table 37-24, “Embedded Flash Wait States,” on page
Note:
The user must ensure that the device is running at the authorized frequency by programming the PLL properly to
not run within the forbidden frequency range.
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx),
General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 256 KB Flash memory, it remains at 10K for the
Flash memory.
None.
Master Clock (MCK)
Non Volatile Memory Bits (NVM Bits)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
ADC: Spurious Clear of EOC Flag
ADC: Sleep Mode
MCK: Limited Master Clock Frequency Ranges
NVM Bits: Write/Erase Cycles Number
It is not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency with only 1 wait state.
582, are still applicable.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
616