AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 280
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AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Price
Company:
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
Quantity:
101
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When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit
rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error
bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the sta-
tus register to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in
the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the
last reset, all bits are transmitted low, as the Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If
new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the
SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the
TDRE bit rises. This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to
be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Regis-
ter, the Shift Register is not modified and the last received character is retransmitted.
Figure 28-9
Figure 28-9. Slave Mode Functional Block Diagram
shows a block diagram of the SPI when operating in Slave Mode.
SPCK
MOSI
NSS
SPIDIS
SPIEN
SPIENS
SPI_CSR0
LSB
NCPHA
CPOL
BITS
Shift Register
Clock
SPI
SPI_RDR
SPI_TDR
RD
TD
MSB
SAM7S Series [DATASHEET]
OVRES
RDRF
TDRE
6175M–ATARM–26-Oct-12
MISO
280
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