AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 485

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 34-4. Non Overlapped Center Aligned Waveforms
Note:
When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the
period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned
channel.
Waveforms are fixed at 0 when:
Waveforms are fixed at 1 (once the channel is enabled) when:
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
• the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
• the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be
• CDTY = CPRD and CPOL = 0
• CDTY = 0 and CPOL = 1
• CDTY = 0 and CPOL = 0
• CDTY = CPRD and CPOL = 1
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
(
--------------------------------------------
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(
-------------------------------------------------------
If the waveform is left aligned then:
If the waveform is center aligned, then:
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx
register. The default mode is left aligned.
2
2
duty cycle
duty cycle
×
×
X
CPRD
See
MCK
×
MCK
CPRD
Figure 34-5 on page 486
PWM0
PWM1
×
=
=
DIVA
)
(
------------------------------------------------------------------------------------------------------------- -
(
-------------------------------------------------------------------------------------------------------------------------------- -
period 1
(
period
)
or
(
-------------------------------------------------------
No overlap
–
2
⁄
×
2
⁄
CPRD
) 1
fchannel_x_clock
–
MCK
Period
for a detailed description of center aligned waveforms.
period
⁄
(
×
period
fchannel_x_clock
DIVB
)
⁄
2
)
×
CDTY
×
CDTY
)
) )
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
485