AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 543
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AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
Quantity:
101
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Figure 36-3. GOVRE and OVREx Flag Behavior
(ADC_CHSR)
(ADC_CHSR)
ADC_LCDR
ADC_CDR0
ADC_CDR1
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE)
flag is set in the Status Register (ADC_SR).
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in
ADC_SR.
The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during
a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
GOVRE
ADTRG
DRDY
OVRE0
EOC0
EOC1
CH0
CH1
Undefined Data
Undefined Data
Conversion
Undefined Data
Conversion
Data A
Data A
Data B
Conversion
SAM7S Series [DATASHEET]
Data B
6175M–ATARM–26-Oct-12
Data C
Read ADC_CDR1
Data C
Read ADC_CDR0
Read ADC_SR
543
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