AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 323

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

30.7
30.7.1
30.7.2
30.7.3
30.7.4
Master Mode
The Master is the device which starts a transfer, generates a clock and stops it.
Figure 30-5. Master Mode Typical Application Block Diagram
The following registers have to be programmed before entering Master mode:
After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-
bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit
following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th
pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the
acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in
the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be
generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data writ-
ten in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the
TXRDY bit is set until a new write in the TWI_THR. When no more data is written into the TWI_THR, the master
generates a stop condition to end the transfer. The end of the complete transfer is marked by the TWI_TXCOMP
bit set to one. See
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
Definition
Application Block Diagram
Programming Master Mode
Master Transmitter Mode
devices in read or write mode.
Rp: Pull up value as given by the I²C Standard
Host with
Interface
TWI
Figure
TWD
TWCK
30-6,
Serial EEPROM
Atmel TWI
Slave 1
Figure
30-7, and
I²C RTC
Slave 2
Figure
30-8.
Controller
I²C LCD
Slave 3
I²C Temp.
SAM7S Series [DATASHEET]
Slave 4
Sensor
Rp
6175M–ATARM–26-Oct-12
Rp
VDD
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