AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 137

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Table 20-20. Signal Description List (Continued)
20.3.2
20.3.3
Signal Name
TST
PGMEN0
PGMEN1
PGMEN2
TCK
TDI
TDO
TMS
The following algorithm puts the device in Serial Programming Mode:
Note:
Table 20-21. Reset TAP Controller and Go to Select-DR-Scan
The read/write handshake is done by carrying out read/write operations on two registers of the device that are
accessible through the JTAG:
• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within T
• Wait for T
• Reset the TAP controller clocking 5 TCK pulses with TMS set.
• Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.
• Shift 0x2 into the DR register (DR is 4 bits long, LSB first) without going through the Run-Test-Idle state.
• Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.
• Debug Comms Control Register: DCCR
• Debug Comms Data Register: DCDR
Entering Serial Programming Mode
Read/Write Handshake
After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock (> 32
kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher
frequency on XIN speeds up the programmer handshake.
TDI
POR_RESET
Xt
X
X
X
X
X
X
Function
Test Mode Select
Test Mode Select
Test Mode Select
Test Mode Select
JTAG TCK
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
.
POR_RESET
TMS
1
1
1
1
1
0
1
+ 32(T
TAP Controller State
Test-Logic Reset
Run-Test/Idle
Select-DR-Scan
SCLK
) if an external clock is available.
JTAG
Test
Output
Type
Input
Input
Input
Input
Input
Input
Input
Active
Level
High
High
High
Low
-
-
-
-
SAM7S Series [DATASHEET]
Comments
Must be connected to VDDIO.
Must be connected to VDDIO
Must be connected to VDDIO
Must be connected to GND
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
6175M–ATARM–26-Oct-12
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