AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 702

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.18.6.10
40.18.6.11
40.18.6.12
40.18.7
40.18.7.1
40.18.7.2
40.18.7.3
None.
The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an SPI enable com-
mand does not set TX_READY, TX_EMPTY flags.
Send SPI disable command after a software reset.
If CSAAT = 1 for current access and there is no more TX request for a time greater than DLYBCT + DLYBCS, then
if an access is requested on another slave, the NPCS bus switches from one CS to the one requested without
DLYBCS. External Slaves may reach a contention on SPI_MISO line for a short period.
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and
the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge
(rising or falling) of synchro has a Start Delay equal to zero.
None.
If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during
data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is
lost. This problem does not exist when generating a periodic synchro.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock
• Transmitting with the slowest chip select and then with the fastest one, then an additional
Synchronous Serial Controller (SSC)
frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SSC: Periodic Transmission Limitations in Master Mode
SPI: Software Reset and SPIEN Bit
SPI: CSAAT = 1 and Delay
SPI: Bad Serial Clock Generation on 2nd Chip Select
SSC: Transmitter Limitations in Slave Mode
SSC: Transmitter Limitations in Slave Mode
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
pulse is generated
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