AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 173

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

23.7.5
23.7.6
The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic oper-
ations. This is necessary when working with a debug system. When a debugger, working either with a Debug
Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the
AIC User Interface and thus the IVR. This has undesirable consequences:
In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC.
This operation is generally not performed by the debug system as the debug system would become strongly intru-
sive and cause the application to enter an undesired state.
This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables
the Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on
the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading
it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the
current interrupt only when AIC_IVR is written.
An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra
AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the
read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC
context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
1. Calculates active interrupt (higher than current or spurious).
2. Determines and returns the vector of the active interrupt.
3. Memorizes the interrupt.
4. Pushes the current priority level onto the internal stack.
5. Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Opera-
tions 4 and 5 are only performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without mod-
ification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as
being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when
AIC_IVR is read. This is most prone to occur when:
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending.
When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register).
The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
• An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short
• An internal interrupt source is programmed in level sensitive and the output signal of the corresponding
• An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the
Protect Mode
Spurious Interrupt
time.
embedded peripheral is activated for a short time. (As in the case for the Watchdog.)
interrupt source.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
173