AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 192

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

25.4
25.5
25.6
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does
not prevent data transfers from other masters of the system bus.
USB Clock Controller
Note: The USB Clock Controller does not pertain to SAM7S32/16.
The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to generate a 48 MHz,
a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLR.
When the PLL output is stable, i.e., the LOCK bit is set:
Figure 25-2. USB Clock Controller
Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral
Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into
the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the
peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically dis-
abled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its
last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the
Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source
number assigned to the peripheral.
Programmable Clock Output Controller
The PMC controls 3 signals to be output on external pins PCKx. Each signal can be independently programmed
via the PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the PLL output and the main clock by writing the
CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the
PRES (Prescaler) field in PMC_PCKx.
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral
when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity
of this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may
be controlled via the Master Clock Controller.
Source
Clock
USB
USBDIV
Divider
/1,/2,/4
UDP
UDP Clock (UDPCK)
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
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