AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 194

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Note:
4. Selection of Master Clock and Processor Clock
• If a new value for CSS field corresponds to PLL Clock,
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s) (Does
not pertain to SAM7S32/16.)
Code Example:
If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL input clock multi-
plied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles.
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow
clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between different values
(1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES
parameter is set to 1 which means that master clock is equal to slow clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the
PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be
raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The preferred programming
sequence for the PMC_MCKR register is as follows:
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to
indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit
to be set again before using the Master and Processor Clocks.
Code Example:
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
write_register(CKGR_PLLR,0x00040805)
IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR the
MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see
Section
25.8.2.
“Clock Switching Waveforms” on page
197.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
194