AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 764

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Version
6175C
Version
6175B
Comments
AT91SAM7S321 addresses
Values given in PIO Line column:
Section 40. ”Errata”
Section 40.6.3.1 ”MCK: Limited Master Clock Frequency Ranges”
Section 40.11.3.1 ”MCK: Limited Master Clock Frequency Ranges”
Section 40.16.3.1 ”MCK: Limited Master Clock Frequency Ranges”
Section 40.21.3.1 ”MCK: Limited Master Clock Frequency Ranges”
and
Section 40.6.4.1 ”NVM Bits: Write/Erase Cycles Number”
Section 40.11.4.1 ”NVM Bits: Write/Erase Cycles Number”
Section 40.16.4.1 ”NVM Bits: Write/Erase Cycles Number”
Section 40.21.4.1 ”NVM Bits: Write/Erase Cycles Number”
note
”Voltage Regulator Mode Register” page
AT91SAM7S321 addresses
Values given in PIO Line column:
Comments
Added to datasheet:
Section 40.6 “SAM7S256 Errata - Manufacturing Number 58818C” on page 614,Section 40.11
“SAM7S128 Errata - Manufacturing Number 58818C” on page
Manufacturing Number 58814G” on page 678 Section 40.21 “SAM7S32 Errata - Manufacturing Number
58814G” on page 716
Changes/updates to the following:
“ADC Characteristics” on page
Characteristics SAM7S512/256/128,” on page 560
on page 570
update to
update to
field definitions in
Section 8. “Memories” on page 18
Evolution in IP blocks:
EFC:
PMC:
DBGU:
SPI:
UDP:
Interface” page
In Features and global:
EmbeddedICE to replace usage of “embedded in-ciruit emulator”
Section 28. ”Serial Peripheral Interface (SPI)” page 1
(2)
FMCN: Flash Microsecond Cycle Number
Section 34.3.2 ”Power Management” page
Section 26.7 ”Programming Sequence” page 215
”ARCH: Architecture Identifier” page 259
added to
“Internal Memory Mapping” on page 98
SVMST0: Saved PDC Abort Source
462,
“MC Abort Status Register” on page
Table 37-24, “Embedded Flash Wait States,” on page 582
added lines and note to the following:
Section 40. “Errata” on page 595
”UDP Transceiver Control Register” page 478
”EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support”
redefined:Table 22-4, “User Area Addresses,” on page 171
redefined:Table 22-4, “User Area Addresses,” on page 171
574,
Table 22-5, “Pins Driven during Boot Program Execution,” on page 171
Table 22-5, “Pins Driven during Boot Program Execution,” on page 171
updated: 2 ms => 3 ms, 10 ms => 15 ms, 4 ms => 6 ms
Figure 37-5
118, bit field name corrected
and
register field in
and
register field in
445,
and
SVMST1: Saved ARM7TDMI Abort Source
Figure 37-6 on page
103.
Section 34.6 ”USB Device Port (UDP) User
Table 37-13, “Phase Lock Loop Characteristics,”
AT91SAM7S256
AT91SAM7S128
AT91SAM7S64
AT91SAM7S32
646,
”MC Flash Mode Register” page 138
“Debug Unit Chip ID Register”
AT91SAM7S256
AT91SAM7S128
AT91SAM7S64
AT91SAM7S32
Section 40.16 “SAM7S64 Errata -
”PSTDBY: Power Standby Mode”
576,
SAM7S Series [DATASHEET]
Table 37-6, “DC Flash
6175M–ATARM–26-Oct-12
register
Change
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#1547 and
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review
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#1217
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05-501
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