AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 758

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Version
6175H
Comments (Continued)
UDP:
Table 35-2, “USB Communication
In the USB_CSR register, the control endpoints are not effected by the fit field,
Disable” on page
Updated: write1 =....in
Updated: write1 =....in
Section 35.6.10 ”UDP Endpoint Control and Status Register”
USB clock and system clock cycle, and updated “note” appearing under the code. “wait 3 USB clock cycles and
3 system clock cycles before accessing DPR from RX_DATAx and TXPKTRDY bit
fields, ditto for RX_DATAx and TXPKTRDY bit field descriptions.”
Section 35.2 ”Block
Clock domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral clock requirements.
Section 35.6 ”USB Device Port (UDP) User
Section 35.6.6 ”UDP Interrupt Mask
USART:
“USCLKS: Clock Selection” on page
Section 31.5.1 ”I/O Lines”
“TXEMPTY: TXEMPTY Interrupt Enable” on page
Section 31.6.2 ”Receiver and Transmitter
resets clear the...”
Section 31.6.5 ”IrDA
Section 31.2 ”Block
Section 31.6.3.1 ”Transmitter
Electrical/Mechanical Characteristics,
Table 37-10, “Main Oscillator
Table 37-12, “XIN Clock Electrical
Figure 37-2 ”XIN Clock Timing”
Section 37.2 ”DC
ADC Characteristics:
Converter Terminology added below table.
Table 38-5, “LQFP and QFN Package Characteristics”
Table 37-7, “Power Consumption for Different
Section 37.6 ”Master Clock
Section 37.7 ”I/O
Section 40.
Section 40.4 ”SAM7S512 Errata - Revision A Parts”
Section 40.8 ”SAM7S256 Errata - Revision B Parts”
Section 40.13 ”SAM7S128 Errata - Revision B Parts”
Section 40.12 ”AT91SAM7S64 Errata - Revision B Parts”
Section 40.22 ”SAM7S32 Errata - Revision A Parts”
Section 40.23 ”SAM7S32 Errata - Revision B Parts”
AT91SAM7S16/161:
Section 40.24 ”SAM7S161 Errata - Revision A Parts”
Section 40.25 ”SAM7S16 Errata - Revision A Parts”
”Errata”, added the following:
Characteristics”, moved from former location.
533,
Characteristics”and
Diagram”, in the text below the block diagram, MCK specified as clock used by Master
Diagram”, signal directions from pads to PIO updated in the block diagrams.
Mode”, updated with instruction to receive IrDA signals.
Table 37-21, “Transfer Characteristics”
“RX_DATA_BK0: Receive Data Bank 0”
“TXPKTRDY: Transmit Packet Ready”
2nd and 3rd paragraphs updated.
Characteristics”, moved from former location.
Characteristics”, added schematic in footnote to C
Operations”, last (4th) paragraph updated.
added below table 36-12
Flow”, Supported Endpoint column updated
Characteristics”, updated
Register”, bit field 12 has been defined as BIT12 and cannot be masked.
391, bit field in US_MR register, DIV=8 in “Selected Clock” column
Section 38. ”Mechanical
Control”, In 4th paragraph, “replaced 2nd sentence: The software
Interface”, The register mapping table has been updated.
Modes”, updated and expanded ARM core clock information.
394, no characters when at 1, updated bit field in US_CSR
provides list of errata with links.
JESD97 Classification updated to be e3.
INL and DN updated, linked reference to Data
update to code and added instructions regarding
bit field of USB_CSR register.
Characteristics”, removed reference to T
bit field of USB_CSR register.
“EPEDS: Endpoint Enable
L
and C
SAM7S Series [DATASHEET]
LEXT
symbols.
6175M–ATARM–26-Oct-12
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