AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 748
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AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Price
Company:
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
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101
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40.25.1.7
40.25.1.8
40.25.1.9
40.25.1.10
40.25.1.11
40.25.2
40.25.2.1
GOVRE should be set but is not.
None
When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being
already active, GOVRE does not rise.
Note:
None
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has been cleared (by a
read of CDRi or LCDR), reading the Status register at the same instant as an end of conversion (causing the set of
EOC status on channel i), does not lead to a reset of the OVRE flag (on channel i) as expected.
None
If a channel is disabled while a conversion is running and if a read of CDR is performed at the same time as an end
of conversion of any channel occurs, the EOC of the channel with the conversion running may rise (whereas it has
been disabled).
Do not take into account the EOC of a disabled channel
If “x” and “y” are two successively converted channels and “z” is yet another enabled channel (“z” being neither “x”
nor “y”), reading CDR on channel “z” at the same instant as an end of conversion on channel “y” automatically
clears EOC[x] instead of EOC[z].
None.
If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after
a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register
(SLEEP) then ADC Control Register (START bit field); to start an analog-to-digital conversion, in order put ADC
into sleep mode at the end of this conversion.
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is
directly modified when writing the Channel Update Register.
• GOVRE inactive,
• previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”.
Pulse Width Modulation Controller (PWM)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
ADC: GOVRE Bit is not Set when Disabling a Channel
ADC: OVRE Flag Behavior
ADC: EOC Set although Channel Disabled
ADC: Spurious Clear of EOC Flag
ADC: Sleep Mode
PWM: Update when PWM_CCNTx = 0 or 1
OVRE[x] rises as expected.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
748
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