AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 700
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Part Number:
AT91SAM7S256D-AU
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ATMEL
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40.18.4.3
40.18.4.4
40.18.4.5
40.18.5
40.18.5.1
40.18.6
40.18.6.1
40.18.6.2
Do not write 0 in the period register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
None.
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode
may change the polarity of the signal.
Do not set PWM_CDTYx at 0 in center aligned mode.
Do not set PWM_CDTYx at 0 or 1 in left aligned mode.
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the
PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel),
the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
Do not disable a channel before completion of one period of the selected clock.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the cor-
responding bit might be cleared. This can lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
If a software reset (SWRSTin the SPI Control Register) is performed, the SPI may not work properly (the clock is
enabled before the chip select.
The SPI Control Register field, SWRST needs to be written twice to be set correctly.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows:
None.
Real Time Timer (RTT)
Serial Peripheral Interface (SPI)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
PWM: Counter Start Value
PWM: Constraints on Duty Cycle Value
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
RTT: Possible Event Loss when Reading RTT_SR
SPI: Software Reset Must be Written Twice
SPI: Pulse Generation on SPCK
– The Baudrate is odd and different from 1
– The Polarity is set to 1
– The Phase is set to 0
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
700
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