AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 510

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 35-8. Data IN Transfer for Ping-pong Endpoint
35.5.2.5
35.5.2.6
TXPKTRDY Flag
(UDP_MCSRx)
FIFO (DPR)
Bank 0
USB Bus
Packets
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Bank 1
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long,
some Data IN packets may be NACKed, reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of
data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints
with ping-pong attributes.
To perform a Data OUT transaction, using a non ping-pong endpoint:
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be
5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has
7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being
Data OUT Transaction
Data OUT Transaction Without Ping-pong Attributes
TXPKTRDY in the endpoint’s UDP_ CSRx register.
sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_ FDRx register.
the endpoint’s UDP_ CSRx register is set. An interrupt is pending while TXCOMP is being set.
prepared the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_ CSRx register.
used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are writ-
ten to the FIFO by the USB device and an ACK is automatically carried out to the host.
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Set by Firmware,
Data Payload Written in FIFO Bank 0
Data IN
PID
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
Written by
Microcontroller
Data IN
Read by USB Device
Cleared by USB Device,
Data Payload Fully Transmitted
Set by USB
Device
ACK
PID
Interrupt Cleared by Firmware
Data IN
PID
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
Written by
Microcontroller
Set by Firmware,
Data Payload Written in FIFO Bank 1
SAM7S Series [DATASHEET]
Read by USB Device
Data IN
Set by USB Device
6175M–ATARM–26-Oct-12
ACK
PID
.
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