AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 153

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

22.3.4
22.3.5
22.4
Table 22-1.
Note:
Offset
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120
0x124
Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data
transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are
loaded into the Counter/Pointer registers in order to re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENDTX) and the end of both cur-
rent and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can
trigger an interrupt request to the AIC.
The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Reg-
ister) is written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then
requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Hold-
ing Register (RHR) and then triggers a write in the memory.
After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decre-
mented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers.
The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each
product.These priorities are defined in the product datasheet.
If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is
determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers
are handled first and then followed by transmitter requests.
Peripheral DMA Controller (PDC) User Interface
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
Data Transfers
Priority of PDC Transfer Requests
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc).
Register
Receive Pointer Register
Receive Counter Register
Transmit Pointer Register
Transmit Counter Register
Receive Next Pointer Register
Receive Next Counter Register
Transmit Next Pointer Register
Transmit Next Counter Register
PDC Transfer Control Register
PDC Transfer Status Register
Register Mapping
Register Name
PERIPH
PERIPH_RCR
PERIPH_TPR
PERIPH_TCR
PERIPH_RNPR
PERIPH_RNCR
PERIPH_TNPR
PERIPH_TNCR
PERIPH_PTCR
PERIPH_PTSR
(1)
_RPR
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Write-only
Read-only
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
0x0
0x0
0x0
0x0
-
0x0
Reset
0x0
0x0
0x0
0x0
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