AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 760

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Version
6175F
Comments
“Features” on page 1
Manchester Encoder/Decoder removed from USART.
“Features” on page
Pinout”Section 39. ”SAM7S Ordering
Section 4.1 ”64-lead LQFP and 64-pad QFN Package Outlines”
pad QFN Package
Figure 8-1 on page 20
Section 20. ”Embedded Flash Controller (EFC)”
Section 10.1 ”User
Table 10-1
ADC Block diagram
”ADC Timings” page 485
Section 21. ”Fast Flash Programming Interface
21.2.5.6, and
Table 21-1 on page 147
AIC,
“Advanced Interrupt Controller (AIC) User Interface”
AT91SAM7 Boot Program
”Flow
DBGU:
Functional Block Diagram in
Register”ice_nreset signal replaced with pad name, Power-on Reset (power_on_reset.)
“Peripheral DMA Controller (PDC)”
“
PIO,
Section 15.4.1 ”Pull-up Resistor
Figure 15-3 ”I/O Line Control Logic” page
”PMC Master Clock Register” on page 231
Note defining PIDx added to
Register” page 226
Table 26-2 on page
PWM, updated waveform generation
RSTC; added info on startup counter on crystal oscillator
RTT, added note to
SPI,
Section 28.6.3 ”Master Mode Operations”
Section 28.7.1 ”SPI Control Register”
page
Section 28.7.9 ”SPI Chip Select Register”
Transfers” page
Section 28.6.3.8 ”Mode Fault Detection”
SSC,
ENDTX”
Section 24.7.3.1 ”Priority Controller”
Figure 28-9 ”Slave Mode Functional Block Diagram” page
Section 15.4.4 ”Output Control”
14.
Section 31.6.6.1 ”Compare Functions”
Diagram”replaced
”ARCH: Architecture Identifier” page
bit field name in
and
Section 21.2.5.7 on page
Table 10-2
25.
Outlines”added (replace Mechanical Overview).
Interface”User Peripherals are mapped between 0xF000 0000 and 0xFFFF EFFF.
1,
”Functional Description” page 73
Figure 35-1 on page 479
222: footnotes reassigned.
and
(global) QFN packages changed to 64- and 48-pad QFN
Table 1-1, “Configuration Summary,” on page
Peripheral and System Controller Memory Mapping has been condensed.
PMD and PGMNVALID bus size for AT91SAM7S32 is [7:0].
Figure 22-1
WARNING”...See the section ADC Characteristics....” typo fixed.
Section 22.5 ”SAM-BA Boot”
SYSIRQ changed to SYSC in “Peripheral Identifiers”
Section 23.3.3 ”Transfer Counters”
Figure 27-1 on page 238
“PMC Peripheral Clock Enable Register”
Control”, ref to resistor value removed.
User interface description updated
and
typo corrected
Section 33.5.3.3 ”Changing the Duty Cycle or the Period” page
Information”and global, AT91SAM7S512 added to product family.
added information to bit description
155,
updated
Figure 22-2 on page 165
SRCTYPTE field is in AIC_SMR register, not AIC_SVR
change to SPI_RDR information
corrected equation in
82, 0 and 1 inverted in the MUX controlled by PIO_MDSR.
Corrected name of bitfield “PRES”
Section 21.3.4.6
259: updated
updated
- dedicated and I/O analog inputs differentiated
(FFPI)”, AT91SAM7S512 instructions added to
EFC0 and EFC1 on AT91SAM7S512 explained.
,
Table 24-2 on page 198
and
SAM-BA boot principle changed
Section 13.3.1 ”Reset Controller Overview”
Section 27.5.12 ”Debug Unit Force NTRST
and
272, FLOAD removed
”DLYBCT: Delay Between Consecutive
and
Section 21.3.4.7 on page
3,
Section 4.3 ”48-lead LQFP and 48-
,
Section 4. ”Package and
page
”PMC Peripheral Clock Disable
”SWRST: SPI Software Reset”
173. Correct typo to
note 2 ref to PID bit fields
SAM7S Series [DATASHEET]
Section 22.2
162.
6175M–ATARM–26-Oct-12
Section
430.
Change
Request
Ref.
#2748
rfo review
#3052
#2830
#2284
#2748
#2512
#2548
#3050
#2832
05-460
05-346
05-497
#3053
#1603
#2468
#2748
#1677
#3005
#2522
#1542
#1543
#1676
IP update
760