AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 722
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AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
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AT91SAM7S256D-AU
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40.21.8
40.21.8.1
40.21.8.2
40.21.8.3
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and
the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge
(rising or falling) of synchro has a Start Delay equal to zero.
None.
If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during
data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is
lost. This problem does not exist when generating a periodic synchro.
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are SAM7S signals, TXD is the delayed data to connect to the
device.
• Transmitting with the slowest chip select and then with the fastest one, then an additional
Synchronous Serial Controller (SSC)
on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SSC: Periodic Transmission Limitations in Master Mode
SSC: Transmitter Limitations in Slave Mode
SSC: Transmitter Limitations in Slave Mode
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
pulse is generated
722
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