AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 191

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

25. Power Management Controller (PMC)
25.1
25.2
25.3
Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user periph-
eral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor.
The Power Management Controller provides the following clocks:
Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided
to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock
provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master
Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The
PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0
until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor.
This feature is useful when switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
Figure 25-1. Master Clock Controller
Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor
Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at
least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR).
• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the
• Processor Clock (PCK), switched off when entering processor in idle mode.
• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI,
• UDP Clock (UDPCK), required by USB Device Port operations. (Does not pertain to SAM7S32/16.)
• Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on
device. It is available to the modules running permanently, such as the AIC and the Memory Controller.
etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral
Clocks are named MCK in the product datasheet.
the PCKx pins.
MAINCK
PLLCK
SLCK
PMC_MCKR
CSS
PMC_MCKR
Master Clock
Prescaler
PRES
SAM7S Series [DATASHEET]
MCK
To the Processor
Clock Controller (PCK)
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